The present invention relates to a statistical simulation apparatus and a simulation method for estimating a variation in delay of an LSI circuit due to variation causes occurring in LSI fabrication processes or the like and utilizing a result of the estimation in simulation of LSI circuit delay.
With development of fabrication technologies, rapid improvements of transistors have been made in terms of size reduction and integration density increase. Accordingly, as for CMIS semiconductor integrated circuit devices (hereinafter, referred to as “LSIs”), devices in which various functions are formed on one chip have been developed in recent years.
When an LSI is developed, a design margin is normally provided during fabrication process steps. There are various factors requiring consideration of a design margin. For example, a variation in electric properties of each transistor constituting a circuit may be caused in fabrication process steps or such a variation may also be caused due to change in an operation environment such as voltage or temperature. Thus, a design margin has to be considered at any time.
As shown in FIG. 22, in general, an LSI can be decomposed into signal paths 200 each including 1st through nth (where n is 1 or an integer larger than 1) stage circuit cells 202 between two flipflops 201.
Each of the circuit cells 202 includes logic circuits such as inverter, NAND and NOR. The logic circuits are connected to each other by an interconnect. In this case, it is required to design an LSI so that a delay caused when a signal is propagated through a series of the circuit cells 202 included in a signal path 200 can be fit within a predetermined period which is determined based on a cycle time of a clock signal 203 (normally, the reciprocal of an operation frequency or a clock frequency, or a period obtained by integrally multiplying the reciprocal). This relationship will be expressed as Equation 1.tcycle≧Σti+K(where i=1, 2, . . . nth integer)  [Equation 1]
In this equation, tcycle indicates a cycle time which is a design target property to be achieved, Σti indicates the total sum of signal propagation delays ti between the input and output terminals of a circuit cell i located between flipslops 201, K indicates the sum of a set-up time of the flipflops 201, a skew of the clock signal 203 and the like.
A design margin is indicated by coefficients for various variation causes for delays which are called “derating factors”. For example, as shown in the following Equation 2, there is a method in which a delay value under the worst condition is simply estimated from a standard (or typical) delay value to achieve a labor saving design. Herein, tworst indicates the worst value for each signal path delay, ttyp indicates a standard value for each signal path delay, P indicates a delay variation coefficient for a delay due to a variation in fabrication process steps, V indicates a delay variation coefficient for a delay due to a power supply voltage range, and T indicates a delay variation coefficient for a delay due to a temperature range. In this case, a standard value for delays of all signal paths in an LSI is first obtained, and then the obtained value is multiplied by each of the derating factors P, V and T to simply obtain a worst value for a design margin. Herein, the right side of Equation 2 corresponds to Σti in Equation 1.
An example for the derating factors is shown in FIG. 23. Assume that P, V and T in Equation 2 are substituted by values shown in FIG. 23. A worst delay value tworst can be obtained from a standard (typ) delay value ttyp based on Equation 3. Moreover, a best delay value tbest can be obtained based on Equation 4 in the same manner. Thus, the operation of an LSI under each of the best and worst conditions can be confirmed at the time of designing.tworst=ttyp×P×V×T  [Equation 2]tworst=ttyp×1.4×1.15×1.1  [Equation 3]tworst=ttyp×0.6×0.85×0.9  [Equation 4]
In an LSI, quality and performance trade off each other. Therefore, it is safe to provide an excessive margin for an LSI, but if so, useless part in a design is increased, so that performance (e.g., operation frequency) is deteriorated.
On the other hand, if a margin is too small, lack of quality increases possibility of causing malfunction. Therefore, unless an appropriate margin, i.e., a not excessive and not too small margin, can be evaluated and an designing environment which allows designing based on the evaluation is provided, it is difficult to effectively develop an LSI, such as recent digital signal processors, which allows great performance and high quality at the same time.
Moreover, with a method in which a design margin is provided based on delay calculation performed by using fixed derating factors for all of the LSI's signal paths, such as the method shown in FIG. 23 using worst conditions, an optimum margin for each signal path can not be evaluated and also can not be set. Therefore, in many cases, an excessive margin as a whole is produced.
Then, a method for statistically calculating delays of an LSI without using derating factors has been known (see U.S. Pat. No. 5,383,167). This is a method in which a variation in delay of a circuit cell included in an LSI, i.e., a delay probability distribution is expressed by a histogram, a delay probability distribution for each circuit cell located along a signal path in the LSI is obtained by operation using obtained histograms, and then precision of a design is evaluated by the obtained variation (probability distribution) in output delay of the signal path. With this method, delay variations according to signal paths can be individually evaluated. Therefore, a design margin can be designed so as not to be excessive or too small, compared to a method in which derating factors are used.
However, in the known LSI delay statistical simulation method described in the above-described United States Patent Publication, a variation in delay of a circuit cell is expressed by a histogram. Therefore, it is possible to give an arbitrary probability distribution (shape) but it is also required to perform operations by carrying out multiple superposed integrations using a histogram in a range of each probability distribution in order to obtain a variation in delay of a signal path. Thus, a problem in which the operation becomes complex arises.
Moreover, another problem is that since a circuit cell has a fixed value for a delay variation and changes in the connection state and layout state of each circuit cell in the LSI are not taken into consideration, reliability of finally obtained operation results is low.
Moreover, in an initial stage of LSI development, there is the demand of understanding of ranges of upper and lower limits for a delay variation even roughly. However, in the known method described above, the ranges of upper and lower limits for a delay variation can not be understood in a simple manner.
Moreover, in the known method, as shown in FIG. 23, a delay variation is assumed to have a symmetrical distribution about the typ value, i.e., variation amounts on either side of the best side and the worst side are the same. In fact, there are cases where the distribution of a delay variation is asymmetrical about the typ value. In such cases, variation amounts on the best side and the worst side are different from each other. This asymmetrical phenomenon can be dealt with by only the above-described complex calculation using a histogram, but it can not be dealt with in a simple manner by using other calculations.